1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device with testing capability.
2. Description of the Background Art
Reflecting the increased scale of integration of semiconductor memory devices, the testing time required to confirm the operation has becomes longer. The time required for testing is extremely increased if the pass/fail determination of memory cells are effected in units of 1 bit each. An approach to reduce the testing time is taken by carrying out the pass/fail determination for a plurality of memory cells at the same time. This method of testing in the units of several memory cells is called “multibit testing”.
Multibit testing is described in detail in, for example, “Ultra LSI Memory”, pp. 183–185 by Kiyoo Ito, published by Baihukan, 1994. A method of multibit testing will be described based on this document.
Referring to FIG. 23 showing the concept of multibit testing, a memory cell array 500 includes X×Y memory cells. Memory array 500 is divided into subarrays #1–#q. Each subarray includes a data input/output line pair GPIO 504, a write driver 503, and a preamplifier 501. One bit line pair is connected to GPIO for every subarray.
In a write operation, all write drivers 503 are rendered active. Test data sent from a terminal DQ0 is transferred to the bit line pair connected to GPIO. Accordingly, test data is written into all the q memory cells located at respective crossings between the bit line pair and activated word line. This is conducted on all word lines and bit line pairs.
In contrast to the general method in which test data is written for each memory cell (for each 1 bit) requiring a writing process of X×Y times, a writing process of only X×Y/q times is required in multibit testing. The writing time of test data can be reduced to 1/q.
In a read mode, all preamplifiers 501 are rendered active at the same time. Test data of the same value are read out simultaneously from the q memory cells located at the crossings of the bit line pair connected to GPIO and the activated word line. The read out test data are transferred to a NOR circuit 502. NOR circuit 502 outputs an H level (logical high) at a terminal DQ1 when all the transmitted data match, and outputs an L level (logical low) at terminal DQ1 when at least one does not match.
In contrast to the general method of reading out test data for every memory cell (for every 1 bit) requiring a read process of X×Y times, the read process is required only X×Y/q times in multibit testing. The time required for reading out test data can be reduced to 1/q.
In such a multibit testing, the time required for testing can further be reduced by increasing the number q of divided subarrays.
However, increasing the number q of subarrays will require a corresponding number of preamplifiers, write drivers, and GPIOs, whereby the circuit scale will become larger. According to the aforementioned document, it is estimated that the value of q in a memory array of X×Y=256 Mbits is 128 at most. With the ever increasing scale of integration in the field of semiconductor memory devices, the need to significantly reduce the testing time is noted.
When data is read out from a memory cell, the potential difference between paired bit lines is amplified by a sense amplifier. The potential difference between the bit lines applied to the sense amplifier may become small due to variation caused by noise or the like. It is desirable that the sense amplifier can properly amplify the potential difference even when of a small level caused by such variation. The need arises for the performance evaluation of whether the sense amplifier can amplify a small potential difference with a simple configuration.